VDA VLSI Design Automation Lab

Department of electronics engineering,
National Chiao Tung University, Taiwan

VDAPlace (ISPD 05/06/11 DAC 12 ICCAD 12)

Participants: Sean Shih-Ying Liu, Ching-Yu Chin, Chuan-Chia Huang, Sheng-De Hu

Description

Vdaplace Vdaplacenr Vdaplacer

This is a joint project aiming to generate high quality placement withing short execution time. Current on-going research supports routability and multi-threaded speed up. Timing is reported on single thread.


Source Code:Trac
# Capo10.5 NTUPlace3 mPL6 SimPL VDAPlace Download
HPWLTime HPWLTime HPWLTime HPWLTime HPWLTime
a1 88.14 25.95 80.93 13.38 77.93 18.36 77.73 2.27 78.36 4.15 adaptec1
a2 100.25 36.06 89.85 13.73 92.04 19.91 90.36 3.48 88.89 5.90 adaptec2
a3 276.80 78.19214.20 29.45214.16 58.92208.95 7.04209.7212.33 adaptec3
a4 231.30 79.32193.74 35.23193.89 55.95187.40 5.30184.2010.80 adaptec4
b1 110.92 41.78 97.28 25.38 96.80 22.82 97.42 4.01 97.33 6.78 bigblue1
b2 162.81 80.55152.20 50.78152.34 61.55145.78 8.28144.2310.52 bigblue2
b3 405.40182.94348.48 94.78344.10 85.23339.7813.79339.7626.95 bigblue3
b41016.19567.15829.16171.33829.44189.83808.2235.80804.4555.08 bigblue4


Related Publication

1. S. Aroonsantidech, Sean S.-Y. Liu, C.-Y. Chin and H.-M. Chen "A Fast Thermal Aware Placement With Accurate Thermal Analysis Based on Green Function". ASP-DAC 2012


Reference

1. M.-C. Kim, D.-J. Lee and I. L. Markov "SimPL: An Effective Placement Algorithm", ICCAD 2010