VDA VLSI Design Automation Lab

Department of electronics engineering,
National Chiao Tung University, Taiwan
Home > Publication > ACM-IEEE-Conference

Category Year Conference Name Title Author Acceptance Rate
ACM-IEEE-Conference 2015 ISPD Closing the Gap between Global and Detailed Placement: Techniques for Improving Routability C.-K. Wang, C.-C. Huang, Sean S.-Y. Liu, C.-Y. Chin, S.-T. Hu, W.-C. Wu and H.-M. Chen
ACM-IEEE-Conference 2015 ASP-DAC An Approach to Anchoring and Placing High Performance Custom Digital Designs Sean S.-Y. Liu, T.-C. Chen, H.-M. Chen
ACM-IEEE-Conference 2014 ICCD Improving Power Delivery Network Design by Practical Methodologies C.-C. Huang, C.-T. Lin, W.-S. Liao, H.-M. Chen, C.-H. Lin, D.-M. Kwai
ACM-IEEE-Conference 2014 ICCAD Planning and Placing Power Clamps for Effective CDM Protection H. C. Lin, Sean S.-Y. Liu and H.-M. Chen
ACM-IEEE-Conference 2014 VLSI-DAT An Automatic Synthesis Tool for Nanometer Low Dropout Regulator Using Simulation Based Model and Geometric Programming Shih-Hsin Hsu, Wei-Zen Chen, Jui-Pin Zheng, Sean S.-Y. Liu, Po-Cheng Pan, and Hung-Ming Chen
ACM-IEEE-Conference 2014 DATE Cost-Effective Decap Selection for Beyond Die Power Integrity Y.-E. Chen, T.-S. Tsai, S.-H. Chen and H.-M. Chen
ACM-IEEE-Conference 2014 ASP-DAC Routability-Driven Bump Assignment for Chip-Package Co-Design M.-L. Chen, T.-H. Tsai, H.-M. Chen and S.-H. Chen
ACM-IEEE-Conference 2013 ICCAD Efficient Analog Layout Prototyping by Layout Reuse with Routing Preservation C.-Y. Chin, P.-C. Pan, T.-C. Chen and H.-M. Chen
ACM-IEEE-Conference 2013 ISPD On the Way to Practical Tools for Beyond Die Codesign and Integration H.-M. Chen (Invited)
ACM-IEEE-Conference 2013 DATE PAGE: Parallel Agile Genetic Exploration toward Utmost Performance for Analog Circuit Design (Accept as Regular) P.-C. Pang H.-C. Lin and H.-M. Chen 24.8% (206/829)
ACM-IEEE-Conference 2013 DATE A Network-Flow Based Algorithm For Power Density Mitigation at Post-Placement Stage (Accept as IP) Sean. S-Y. Liu, R.-G. Lo and H.-M. Chen 36.4% (302/829)
ACM-IEEE-Conference 2013 DATE Effective Power Network Prototyping via Statistical-Based Clustering and Sequential Linear Programming (Accept as Regular) Sean S.-Y. Liu, C.-J. Lee, C.-C. Huang, H.-M. Chen 24.8% (206/829)
ACM-IEEE-Conference 2012 ICCAD Configurable Analog Routing Methodology via Technology and Design Constraint Unification P.-C. Pan,H.-M. Chen, Y.-K. Cheng, J. Liu and W.-Y. Hu 24%
ACM-IEEE-Conference 2012 ISQED Hierarchical Power Network Synthesis for Multiple Power Domain Designs (Accepted as Regular Paper) C.-J. Lee, Sean S.-Y. Liu, C.-C. Huang and H.-M. Chen
ACM-IEEE-Conference 2012 DATE On Effective Flip-Chip Routing via Pseudo Single Redistribution Layer (Accepted as Regular Paper) H.-W. Hsu, M.-L. Chen and H.-M. Chen 27% (250/950)
ACM-IEEE-Conference 2012 DATE Agglomerative Based Flip-Flop Merging for Power Optimization (Accepted as Regular Paper) Sean S.-Y. Liu, C.-J. Lee and H.-M. Chen 27% (250/950)
ACM-IEEE-Conference 2012 ISPD On Constructing Low Power and Robust Clock Tree via Slew Budgeting (Accepted as Regular Paper) Y.-C. Chang, C.-K. Wang and H.-M. Chen 30.77% (20/65) <br> 17 Regular 3 Short
ACM-IEEE-Conference 2012 ASP-DAC A Fast Thermal Aware Placement With Accurate Thermal Analysis Based On Green Function (Accepted as Regular Paper) S. Aroonsantidecha, Sean S.-Y. Liu, C.-Y. Chin, H.-M. Chen 33.11% (99/299)
ACM-IEEE-Conference 2011 ICCAD Fast Analog Layout Prototyping for Nanometer Design Migration Y.-P. Weng, H.-M. Chen, T.-C. Chen, P.-C. Pan, C.-H. Chen, and W.-Z. Chen 30.37% (106/349)
ACM-IEEE-Conference 2011 ISQED Clock Planning for Multi-Voltage and Multi-Mode Designs C.-C. Tsai, T.-H. Lin, S.-H. Tsai 43.45% (126/290) <br>92 Regular 34 Poster
ACM-IEEE-Conference 2011 ISQED Integrated Hierarchical Synthesis of Analog/RF Circuits with Accurate Performance Mapping K.-H. Meng, P.-C. Pan, and H.-M. Chen 43.45% (126/290) <br>92 Regular 34 Poster
ACM-IEEE-Conference 2011 ISQED Mixed Non-Rectangular Block Packing for Non-Manhattan Layout Architectures M.-C. Wu, H.-M. Chen, and J.-Y. Jou 43.45% (126/290)<br>92 Regular 34 Poster
ACM-IEEE-Conference 2011 DATE On Routing Fixed Escaped Boundary Pins for High Speed Boards T.-Y. Tsai, R.-J. Lee, C.-Y. Chin, C.-Y. Kuan 27.02% (211/781)
ACM-IEEE-Conference 2010 SOCC Simultaneous Voltage Island Generation and Floorplanning H.-Y. Li, H.-R. Iris Jiang, and H.-M. Chen
ACM-IEEE-Conference 2010 ASP-DAC Technology Mapping with Crosstalk Noise Avoidance F.-Y. Fan, H.-M. Chen, and I-M. Liu 33.82% (115/340)
ACM-IEEE-Conference 2009 ASQED On Minimizing Various Sources of Noise and Meeting Symmetry Constraint in Mixed-Signal SoC Floorplan Design C.-H. Lin and H.-M
ACM-IEEE-Conference 2009 GLVLSI A Stochastic-Based Efficient Critical Area Extractor on OpenAccess Platform B.-C. Chen, H.-M. Chen, L.-D. Huang, and P.-C. Pan 28.84% (62/215)<br> 34 Regular 28 Short
ACM-IEEE-Conference 2009 VLSI-DAT Coupling- and ECP-Aware Metal Fill for Improving Layout Uniformity in Copper CMP Y.-L. Ko, H.-M. Chen, and Y.-K. Cheng
ACM-IEEE-Conference 2009 DATE Package Routability- and IR-Drop-Aware Finger/Pad Assignment in Chip-Package Co-Design C.-H. Lu, H.-M. Chen, C.-N. Liu, and W.-Y. Shih 23.42% (226/965)
ACM-IEEE-Conference 2009 ISQED Buffer/Flip-Flop Block Planning for Power-Integrity-Driven Floorplanning H.-H. Pan, H.-M. Chen, and C.-Y. Chang 45.67% (137/300) <br>87 Regular 50 Poster
ACM-IEEE-Conference 2008 GLVLSI Efficient and Optimal Post-Layout Double-Cut Via Insertion by Network Relaxation and Min-Cost Maximum Flow, L.-C. Wei, H.-M. Chen, L.-D. Huang, and S. Xu 40.45% (89/200) <br>54 Regular 35 Poster
ACM-IEEE-Conference 2008 VLSI-DAT On Minimizing Topography Variation in Multi-Layer Oxide CMP Manufacturability C.-H. Shui and H.-M. Chen
ACM-IEEE-Conference 2008 ISPD Blockage and Voltage Island-Aware Dual-Vdd Buffered Tree Construction Bruce Tseng and H.-M. Chen 33.33% (20/60)
ACM-IEEE-Conference 2008 ISQED An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign M.-F. Lai and H.-M. Chen
ACM-IEEE-Conference 2007 ICCAD A Selective Pattern-Compression Scheme for Power and Test-Data Reduction C.-Y. Lin and H.-M. Chen 27.25% (139/510)
ACM-IEEE-Conference 2007 SOCC Using Power Gating Techniques in Area-Array SoC Floorplan Design C.-Y. Yeh, H.-M. Chen, L.-D. Huang, W.-T. Wei, C.-H. Lu, and C.-N. Liu
ACM-IEEE-Conference 2007 VLSI-DAT Microarchitecture-Aware Floorplanning for Processor Performance Optimization C.-Y. Chen, J.-D. Huang, and H.-M. Chen
ACM-IEEE-Conference 2007 ASP-DAC On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design C.-H. Lu, H.-M. Chen, and C.-N. Liu 32.11% (131/408)
ACM-IEEE-Conference 2007 ASP-DAC Fast Flip-Chip Pin-Out Designation by Pin-Block Design and Floorplanning for Package-Board Codesign R.-J. Lee, M.-F. Lai, and H.-M. Chen 32.11% (131/408)
ACM-IEEE-Conference 2006 SOCC Performance Constraints Aware Voltage Island Generation in SoC Floorplan Design M.-C. Lu, M.-C. Wu, H.-M. Chen, and H.-R. Jiang 31.37% (53/169)
ACM-IEEE-Conference 2006 SOCC On Achieving Low-Power SoC Clock Tree Synthesis by Transition Time Planning via Buffer Library Study H.-L. Chen and H.-M. Chen 31.37% (53/169)
ACM-IEEE-Conference 2006 VLSI-DAT Multilevel Large-Scale Modules Placement with Refined Neighborhood Exchange K.-C. Wang and H.-M. Chen
ACM-IEEE-Conference 2006 VLSI-DAT Design Migration from Peripheral ASIC Design to Area-IO Flip-Chip Design by Chip I/O Planning and Legalization C.-Y. Chang and H.-M. Chen
ACM-IEEE-Conference 2006 ISQED On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design L.-C. Hsu and H.-M. Chen 36.33% (93/256) 93 <br> Regular
ACM-IEEE-Conference 2005 ISQED Current Calculation on Signal Interconnects M. Shao, Y. Gao, L. Yuan, M.D.F. Wong, and H.-M. Chen 37.39% (83/222) <br> 83 Regular
ACM-IEEE-Conference 2004 ICCD I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design H.-M. Chen, I-M. Liu, M.D.F. Wong, M. Shao, and L.-D. Huang
ACM-IEEE-Conference 2003 DATE Global Wire Bus Configuration with Minimum Delay Uncertainty L.-D. Huang, H.-M. Chen, and D.F. Wong
ACM-IEEE-Conference 2003 ASP-DAC Floorplanning with Power Supply Noise Avoidance H.-M. Chen, L.-D. Huang, I-M. Liu, M. Lai, and D.F. Wong
ACM-IEEE-Conference 2001 GLSVLSI Faster and More Accurate Wiring Evaluation for Interconnect-Centric Floorplanning H.-M. Chen, D.F. Wong, W.-K. Mak, and H.H. Yang
ACM-IEEE-Conference 2001 ASP-DAC Integrated Power Supply Planning and Floorplanning I-Min Liu, H.-M. Chen, T.-L. Chou, A. Aziz, and D.F. Wong
ACM-IEEE-Conference 1999 ICCAD Integrated Floorplanning and Interconnect Planning H.-M. Chen, H. Zhou, F.Y. Young, D.F. Wong, H.H. Yang, and N. Sherwani