VDA VLSI Design Automation Lab

Department of electronics engineering,
National Chiao Tung University, Taiwan
Home > Project > On Increasing Design Reliability in Advanced Manufacturing Technology–Main Project and Subpro- ject 3: Yield Improvement Methodologies in Post-Layout Design Flow and Design for Test

Project Description
Project Name On Increasing Design Reliability in Advanced Manufacturing Technology–Main Project and Subpro- ject 3: Yield Improvement Methodologies in Post-Layout Design Flow and Design for Test
Project Type
Project Source NSC (國科會)
Starting Date August 2006
Ending Date July 2009
Project Description
Project Member
Project Fund