VDA VLSI Design Automation Lab

Department of electronics engineering,
National Chiao Tung University, Taiwan
Home > Member > Master > Yun-Ta Lin

Basic Information

Pic Degree Gender Entry Year Name English Name
Jackou Master M 2004 林昀達 Yun-Ta Lin
Email Occupation
gwing_lin@springsoft.com 新思科技(Synopsys)
Thesis
On Reducing Clock Network Power Consumption by Low-Swing DME Buffering Technique


Publication

Category Year Conference Name Title Author
Other-Conference 2007 SASIMI Low-Power Clock Tree Synthesis by Low-Swing Techniques Y.-T. Lin and H.-M. Chen