VDA VLSI Design Automation Lab

Department of electronics engineering,
National Chiao Tung University, Taiwan
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Basic Information

Pic Degree Gender Entry Year Name English Name
Yehchi Master F 2009 張業琦
Email Occupation
yehchi0604@gmail.com 台灣積體電路公司
Thesis
Robust Clock Tree Synthesis on ISPD 2010 Benchmark


Publication

Category Year Conference Name Title Author
ACM-IEEE-Journal 2014 TODAES Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation C.-K. Wang, Y.-C. Chang, H.-M. Chen and C.-Y. Chin
ACM-IEEE-Conference 2012 ISPD On Constructing Low Power and Robust Clock Tree via Slew Budgeting (Accepted as Regular Paper) Y.-C. Chang, C.-K. Wang and H.-M. Chen


Honorable Mention

Year Title Content
2010 書卷獎

恭賀張業琦同學榮獲99上電子所書卷獎





Responsible Course TA

Date Course Name Designed Labs Grad/Under
2009 Computer Programming I Designed Labs

Undergraduate