VDA VLSI Design Automation Lab

Department of electronics engineering,
National Chiao Tung University, Taiwan
Home > Member > Master > Wan-Ting Lo

Basic Information

Pic Degree Gender Entry Year Name English Name
Aaa Master F 2008 羅琬婷 Wan-Ting Lo
Email Occupation
soul9657@gmail.com 台灣積體電路公司
Thesis
Cosynthesis of Clock Tree and Flip-Flop Redistribution


Publication

Category Year Conference Name Title Author
ACM-IEEE-Journal 2013 TODAES Agglomerative-Based Flip-Flop Merging and Relocation for Signal Wirelength and Clock Tree Optimization Sean S.-Y. Liu, W.-T. Lo, C.-J. Lee, H.-M. Chen