VDA VLSI Design Automation Lab

Department of electronics engineering,
National Chiao Tung University, Taiwan
Home > Member > Post-Doc > Ren Jie, Lee

Basic Information

Pic Degree Gender Entry Year Name English Name
Rjlee Post-Doc M 2005 李仁傑 Ren Jie, Lee
Email Occupation
rjlee@vda.ee.nctu.edu.tw Post-Doc
Thesis
-


Publication

Category Year Conference Name Title Author
ACM-IEEE-Journal 2013 TODAES A study of row-based area-array I/O design planning in concurrent chip-package design flow R.-J. Lee, H.-M. Chen
ACM-IEEE-Journal 2013 TVLSI Board and Chip Aware Package Wire Planning R.-J Lee, H.-W. Hsu and H.-M. Chen
ACM-IEEE-Conference 2011 DATE On Routing Fixed Escaped Boundary Pins for High Speed Boards T.-Y. Tsai, R.-J. Lee, C.-Y. Chin, C.-Y. Kuan
ACM-IEEE-Journal 2010 TVLSI Efficient Package Pin-Out Planning with System Interconnects Optimization for Package-Board Codesign R.-J. Lee and H.-M. Chen
Other-Conference 2008 VLSI-CAD Wirelength-Driven Flip-Chip Pin-Out Designation by Range Constrained Pin-Block Planning in PCB-Package Codesign R.-J. Lee, C.-L. Weng, and H.-M. Chen
ACM-IEEE-Journal 2007 TVLSI Fast Flip-Chip Pin-Out Designation Respin for Package-Board Codesign R.-J. Lee and H.-M. Chen
ACM-IEEE-Conference 2007 ASP-DAC Fast Flip-Chip Pin-Out Designation by Pin-Block Design and Floorplanning for Package-Board Codesign R.-J. Lee, M.-F. Lai, and H.-M. Chen


Honorable Mention

Year Title Content
2010 博士論文獎

恭賀李仁傑同學獲得交大電子所畢業論文優等獎