VDA VLSI Design Automation Lab

Department of electronics engineering,
National Chiao Tung University, Taiwan
Home > Member > Master > Yi-Peng Weng

Basic Information

Pic Degree Gender Entry Year Name English Name
Landorious Master F 2009 翁逸芃 Yi-Peng Weng
Email Occupation
yipeng0610@gmail.com 台灣積體電路公司
Thesis
A Low Power and Robust Clock Tree Through Slew Budgeting


Publication

Category Year Conference Name Title Author
ACM-IEEE-Conference 2011 ICCAD Fast Analog Layout Prototyping for Nanometer Design Migration Y.-P. Weng, H.-M. Chen, T.-C. Chen, P.-C. Pan, C.-H. Chen, and W.-Z. Chen


Honorable Mention

Year Title Content
2010 書卷獎

恭賀翁逸芃同學榮獲99下電子所書卷獎





Responsible Course TA

Date Course Name Designed Labs Grad/Under
2009 Computer Programming I Designed Labs

Undergraduate