VDA VLSI Design Automation Lab

Department of electronics engineering,
National Chiao Tung University, Taiwan
Home > Member > Master > Huang Liang, Chen

Basic Information

Pic Degree Gender Entry Year Name English Name
Danny Master M 2003 陳皇良 Huang Liang, Chen
Email Occupation
Dennyhl.chen@mic.com.tw 神達電腦
Thesis
Low Power Buffered Clock Tree Synthsis Considering Buffer Transition Time


Publication

Category Year Conference Name Title Author
ACM-IEEE-Conference 2006 SOCC On Achieving Low-Power SoC Clock Tree Synthesis by Transition Time Planning via Buffer Library Study H.-L. Chen and H.-M. Chen
Other-Conference 2005 VLSI-CAD Low Power Buffered Clock Tree Synthesis Considering Buffer Transition Time H.-L. Chen and H.-M. Chen