VDA VLSI Design Automation Lab

Department of electronics engineering,
National Chiao Tung University, Taiwan
Home > Member > Master > Hsin Hua, Pan

Basic Information

Pic Degree Gender Entry Year Name English Name
Oscar Master M 2005 潘信華 Hsin Hua, Pan
Email Occupation
oscar_721@msn.com 安仲科技
Thesis
Buffer/Flip-Flop Block Planning for Power-Integrity-Driven Floorplanning


Publication

Category Year Conference Name Title Author
ACM-IEEE-Conference 2009 ISQED Buffer/Flip-Flop Block Planning for Power-Integrity-Driven Floorplanning H.-H. Pan, H.-M. Chen, and C.-Y. Chang