VDA VLSI Design Automation Lab

Department of electronics engineering,
National Chiao Tung University, Taiwan
Home > Member > Master > Chih-Yi Yeh

Basic Information

Pic Degree Gender Entry Year Name English Name
Dark Master M 2004 葉志益 Chih-Yi Yeh
Email Occupation
darkapril@hotmail.com 智成電子
Floorplanning with Sleep Transistors Insertion in the Presence of Power Supply Noise for Low Power


Category Year Conference Name Title Author
ACM-IEEE-Conference 2007 SOCC Using Power Gating Techniques in Area-Array SoC Floorplan Design C.-Y. Yeh, H.-M. Chen, L.-D. Huang, W.-T. Wei, C.-H. Lu, and C.-N. Liu