VDA VLSI Design Automation Lab

Department of electronics engineering,
National Chiao Tung University, Taiwan
Home > Member > Master > Chuan-Chia, Huang

Basic Information

Pic Degree Gender Entry Year Name English Name
Chuan Master M 2011 黃川嘉 Chuan-Chia, Huang
Email Occupation
chuan.ee96@gmail.com 聯詠科技
Thesis
-


Publication

Category Year Conference Name Title Author
ACM-IEEE-Conference 2015 ISPD Closing the Gap between Global and Detailed Placement: Techniques for Improving Routability C.-K. Wang, C.-C. Huang, Sean S.-Y. Liu, C.-Y. Chin, S.-T. Hu, W.-C. Wu and H.-M. Chen
ACM-IEEE-Conference 2013 DATE Effective Power Network Prototyping via Statistical-Based Clustering and Sequential Linear Programming (Accept as Regular) Sean S.-Y. Liu, C.-J. Lee, C.-C. Huang, H.-M. Chen
ACM-IEEE-Conference 2012 ISQED Hierarchical Power Network Synthesis for Multiple Power Domain Designs (Accepted as Regular Paper) C.-J. Lee, Sean S.-Y. Liu, C.-C. Huang and H.-M. Chen


Honorable Mention

Year Title Content
2013 斐陶斐

[賀] 黃川嘉同學入選為 交大斐陶斐會員

2012 ICCAD Routability Driven Contest

恭賀劉時穎,秦敬雨, 胡盛德,黃川嘉 Team VDAPlace獲得 2012 ICCAD Placement Contest 第四名

2012 教育部IC/CAD競賽

恭賀劉時穎,秦敬雨, 胡盛德,黃川嘉 Team VDAPlace獲得 2012 IC/CAD 競賽 特優

2011 書卷獎

恭賀黃川嘉同學榮獲100下電子所書卷獎

2011 優良教學助理獎

恭賀黃川嘉同學榮獲100學年度交通大學優良教學助理獎





Responsible Course TA

Date Course Name Designed Labs Grad/Under
2012 Digital Circuit and System Designed Labs

Undergraduate