VDA VLSI Design Automation Lab

Department of electronics engineering,
National Chiao Tung University, Taiwan
Home > Member > PhD > Chao-Hung Lu

Basic Information

Pic Degree Gender Entry Year Name English Name
Jackou PhD M 2005 呂昭宏 Chao-Hung Lu
Email Occupation
chlu@ee.ncu.edu.tw Alumni
Thesis
VLSI Design Planning with Power Integrity and I/O Constraints


Publication

Category Year Conference Name Title Author
Other-Journal 2011 JISE Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits C.-H. Lu, H.-M. Chen, and C.-N. Liu
ACM-IEEE-Conference 2009 DATE Package Routability- and IR-Drop-Aware Finger/Pad Assignment in Chip-Package Co-Design C.-H. Lu, H.-M. Chen, C.-N. Liu, and W.-Y. Shih
ACM-IEEE-Journal 2008 TODAES Effective Decap Insertion in Area-Array SoC Floorplan Design C.-H. Lu, H.-M. Chen, and C.-N. Liu
Other-Journal 2008 JISE An Effective Decap Insertion Method Considering Power Supply Noise During Floorplanning C.-H. Lu, H.-M. Chen, and C.-N. Liu
ACM-IEEE-Conference 2007 ASP-DAC On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design C.-H. Lu, H.-M. Chen, and C.-N. Liu
Other-Conference 2007 SASIMI An I/O Planning Method for Three-Dimensional Integrated Circuits C.-H. Lu, H.-M. Chen, C.-N. Liu, and W.-Y. Shih