VDA VLSI Design Automation Lab

Department of electronics engineering,
National Chiao Tung University, Taiwan
Home > Member > Master > Chia-Yi Chang

Basic Information

Pic Degree Gender Entry Year Name English Name
Chaiyi Master M 2003 張加易 Chia-Yi Chang
Email Occupation
Louver0205@hotmail.com 瑞昱科技
Thesis
Performance Driven I/O Buffer Block Planning with Core Placement in Flip-Chip Design


Publication

Category Year Conference Name Title Author
ACM-IEEE-Conference 2009 ISQED Buffer/Flip-Flop Block Planning for Power-Integrity-Driven Floorplanning H.-H. Pan, H.-M. Chen, and C.-Y. Chang
Other-Conference 2009 SASIMI IR-Drop-Aware Buffer/Flip-Flop Station Planning in Floorplan Design H.-H. Pan, H.-M. Chen, and C.-Y. Chang
ACM-IEEE-Journal 2008 TVLSI Design Migration from Peripheral ASIC Design to Area-IO Flip-Chip Design by Chip I/O Planning and Legalization Chia-Yi Chang and H.-M. Chen
ACM-IEEE-Conference 2006 VLSI-DAT Design Migration from Peripheral ASIC Design to Area-IO Flip-Chip Design by Chip I/O Planning and Legalization C.-Y. Chang and H.-M. Chen