VDA VLSI Design Automation Lab

Department of electronics engineering,
National Chiao Tung University, Taiwan
Home > Member > PhD > Chia Yi, Lin

Basic Information

Pic Degree Gender Entry Year Name English Name
Chiayi PhD M 2004 林佳毅 Chia Yi, Lin
Email Occupation
chiayi@mail.nctu.edu.tw Alumni
Thesis
On Reducing Test Cost in Modern VLSI Designs


Publication

Category Year Conference Name Title Author
Other-Journal 2011 JISE A Generic Multi-Dimensional Scan-Control Scheme for Test-Cost C.-Y. Lin and H.-M. Chen
Other-Journal 2010 IEICE On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques C.-Y. Lin, L.-C. Hsu, and H.-M. Chen
Other-Journal 2009 IJEE A Methodology with Selective Pattern Compression Schemes on Reducing Test Power and Test Volume C.-Y. Lin, H.-C. Lin, and H.-M. Chen
ACM-IEEE-Conference 2009 ISQED Buffer/Flip-Flop Block Planning for Power-Integrity-Driven Floorplanning H.-H. Pan, H.-M. Chen, and C.-Y. Chang
ACM-IEEE-Journal 2009 TVLSI On Reducing Test Power and Test Volume by Effective Pattern Compression Schemes C.-Y. Lin, H.-C. Lin, and H.-M. Chen
Other-Conference 2009 SASIMI IR-Drop-Aware Buffer/Flip-Flop Station Planning in Floorplan Design H.-H. Pan, H.-M. Chen, and C.-Y. Chang
Other-Conference 2009 VLSI-CAD A Novel Two-Dimensional Scan-Control Scheme for Test-Cost Reduction C.-Y. Lin and H.-M. Chen
ACM-IEEE-Journal 2008 TVLSI Design Migration from Peripheral ASIC Design to Area-IO Flip-Chip Design by Chip I/O Planning and Legalization Chia-Yi Chang and H.-M. Chen
ACM-IEEE-Conference 2007 ICCAD A Selective Pattern-Compression Scheme for Power and Test-Data Reduction C.-Y. Lin and H.-M. Chen
ACM-IEEE-Conference 2006 VLSI-DAT Design Migration from Peripheral ASIC Design to Area-IO Flip-Chip Design by Chip I/O Planning and Legalization C.-Y. Chang and H.-M. Chen


Honorable Mention

Year Title Content
2010 博士論文獎

恭賀林佳毅同學獲得交大電子所畢業論文佳作獎