VDA VLSI Design Automation Lab

Department of electronics engineering,
National Chiao Tung University, Taiwan
Home > Member > Master > Bruce Tseng

Basic Information

Pic Degree Gender Entry Year Name English Name
Bbruce Master M 2004 曾柏欽 Bruce Tseng
Email Occupation
bbruce@ms93.url.com.tw 聯發科技
Thesis
An Efficient Algorithm for Voltage Island Aware Buffered Routing Tree Construction


Publication

Category Year Conference Name Title Author
Other-Journal 2008 IJEE Dual-Vdd Voltage Island-Aware Buffered Routing Tree Construction Bruce Tseng and H.-M. Chen
ACM-IEEE-Conference 2008 ISPD Blockage and Voltage Island-Aware Dual-Vdd Buffered Tree Construction Bruce Tseng and H.-M. Chen
Other-Conference 2006 VLSI-CAD On Achieving Low Power Buffered Routing Tree Construction in the Presence of Dual-Vdd Voltage Islands Bruce Tseng and H.-M. Chen