VDA VLSI Design Automation Lab

Department of electronics engineering,
National Chiao Tung University, Taiwan

Congratulations to Chen Chen of winning the Fourth Place of ISPD 2017 Contest : Clock-Aware FPGA Placement

ISPD 2017 Contest : Clock-Aware FPGA Placement

Ranking Team Affilication
1st UTPlaceF2.0 University of Austin Texas
2nd NTUfplace National Taiwan University
3rd RippleFPGA Chinese University of Hong Kong
4th VDAPlacer National Chiao Tung University
5th GPlace University of Guelph, Canada

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Post time:2017-10-16 00:11:32 UTC